In the manufacture of bipolar transistors, the trend in the semiconductor industry is to increase the switching speed performance of such transistors. It is well known in the art, though, that the performance of a bipolar transistor is limited by the maximum oscillating frequency of the device. Parasitic resistance in both the base and the emitter of the transistor tend to limit the maximum oscillation frequency of the device, effectively limiting the switching speed. Therefore, a reduction in the resistance of the base, the emitter, or both, will increase the performance of the device. Particularly with the development of wireless and broadband applications, and as transistor switching speeds exceed 350 GHz, it is crucial to lower the parasitic resistance in order to increase the performance of the device.
In the prior art, the extrinsic base region of a typical hetero-junction bipolar transistor is formed of doped Polysilicon, and may be covered with a Silicide region, also known as a salicide region. As transistors are scaled to ever-smaller dimensions though, the parasitic resistance of such a device becomes large relative to its intrinsic resistance.
Additionally, it is important that any method of fabricating bulk quantities of such transistors be as efficient as possible. For this reason, it is desirable that a method of manufacture employ materials that are compatible with conventional Silicon processes, and that the method has as little complexity as possible and results in a low defect rate.
In view of the foregoing, there is a need in the art for an improved transistor having a higher maximum oscillation frequency, and a simple and reliable method of fabricating such a transistor.